All posts tagged "computer-architecture"
Address-coded endian
Many years ago I found in an old Arm manual a description of the permutation that would happen to a 32-bit word loaded from an un-aligned offset. I don’t recall what the pattern was, but it looked like the barrel shifter had been repurposed to handle sub-word addressing of bytes and then masking deferred because it was a full-width read, even though the address was rounded down.
Naturally-aligned compressed opcode encoding
In the world of fixed-length instruction sets, the addition of compressed instructions (no-longer fixed-length instructions) is kind of a nuisance. Arm dropped them when they went to AArch64, and there was a proposal to make them optional in RISC-V but it didn’t fly.
Hinting train of branch directions in advance
Long ago I had to do a scaling operation which would yield a stream of branch decisions based on whether or not a row pointer would advance and need the subsequent row to be recalculated. I decided to try to calculate the branch decisions well in advance, and shift them into a shift register and then to branch on the least significant bit of that register and then do a right-shift to schedule the next branch decsion. I think the code is in AOSP somewhere.
A Latin-Square-based L1 cache layout
If I were going to build some kind of fantasy machine I would not fuss about making it high-performance. Mine would just be a mash-up of random things I found interesting at some point.
A reasonably effective hash instruction
As per part one of this post, I have reasoned through and tested a proof of concept for generic CPU instruction which could achieve most of the required mixing of a good hash function in a single cycle (working with a combinational depth of 20 to 24 gates as a guide).
Why I want a dedicated hash instruction
A good hash function is expected to remove correlations of various sorts between subsets of inputs and their hashed outputs in order to mitigate the risk of those correlations producing performance aberrations (cache collisions, unbalanced structures, etc.) or statistical biases.
Idly musing over RowHammer mitigation strategies
Watching a RowHammer talk (slides) a while back (not actually the linked one, but I couldn’t find the one I attended) left me with a couple of thoughts about possible mitigations which I didn’t see discussed.
All posts tagged "endian"
All posts tagged "memory"